Memory Information?

[Razor]

spd bus specification http://www.rambus.com/assets/documen...40-SPDSpec.pdf

Delphi-Quellcode:

unit Memory;

interface



type
  DWord = LongWord;

  tCtrl_Info = packed record
    index, poll, cap, mode: integer;
    dwBus, dwDev, dwFunc: DWord;
  end;

  tTimings = packed record
    CAS, RCD, RP, RAS: single;
  end;

  tgRAMInfo = packed record
    DRAMClock: double;
    RamSize: DWord;
    DRAMCoef, DRAMCnls, DRAMType, DRAMAccel: string;
  end;

  tGetFSBMethod = procedure (lCPUClock, FSB: double; Mult: single; var GRAMInfo: tGRAMInfo);
  tGetTmngsMethod = procedure (var Timings: tTimings; var gRAMInfo: tGRAMInfo);
  tSetupECCMethod = procedure;

  Memory_Controller = packed record
     VendorID, DeviceID: Word;
     name: string;
     tested: integer;
    GetFSBMethod: tGetFSBMethod;
    GetTmngsMethod: tGetTmngsMethod;
    SetupECCMethod: tSetupECCMethod;
  end;

  cMemory = class
  private
  public
    fCtrl_Info: tCtrl_Info;
    fTimings: tTimings;
    fgRAMInfo: tgRAMInfo;

    constructor Create;
    destructor Destroy; override;

    procedure DetectMemCtrl;
    function GetPhysMemSize: DWord;
    procedure FillMemCtrlInfo(lCPUClock, FSB: double; Mult: single);
  end;

var
  MemInfo: cMemory;

implementation

uses SysUtils, Windows, Dialogs;

//nVidia nForce 2 Methods
procedure poll_fsb_nf2(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
  mempll: DWord;
  mem_m, mem_n: byte;
begin
  //Get the coef (COEF = N/M) - Here is for Crush17
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 3, $70, mempll);
   mem_m:=mempll and $0F;
   mem_n:=(mempll shr 4) and $0F;

  //ShowMessage(format('%x', [oHWIO.MemReadLong($5620)]));


  //If something goes wrong, the chipset is probably a Crush18
   if (mem_m = 0) or (mem_n = 0) then
  begin
      GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 3, $7C, mempll);
      mem_m:=mempll and $0F;
      mem_n:=(mempll shr 4) and $0F;
   end;

  //Computing DRAM Frequency
  gRAMInfo.DRAMClock:=FSB*(mem_n/mem_m);

  //Forming DRAM : FSB Divider
  if (mem_n = mem_m) then gRAMInfo.DRAMCoef:='1:1'
                     else gRAMInfo.DRAMCoef:=IntToStr(mem_m)+':'+IntToStr(mem_n);
end;

procedure poll_timings_nf2(var Timings: tTimings; var gRAMInfo: tGRAMInfo);
var
  dramtlr, dramtlr2, dramtlr3, temp: DWord;
   dimm1p, dimm2p, dimm3p: DWord;
begin
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 1, $90, dramtlr);
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 1, $A0, dramtlr2);
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 1, $84, dramtlr3);
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 2, $40, dimm1p);
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 2, $44, dimm2p);
  GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 2, $48, dimm3p);

  //CAS Latency (tCAS)
   temp:=(dramtlr2 shr 4) and $7;
  if (temp = $2) then Timings.CAS:=2
  else if (temp = $6) then Timings.CAS:=2.5
  else if (temp = $3) then Timings.CAS:=3;

   //RAS-To-CAS (tRCD)
   Timings.RCD:=(dramtlr shr 20) and $F;

   //RAS Precharge (tRP)
   Timings.RP:=(dramtlr shr 28) and $F;

   //RAS Active to precharge (tRAS)
   Timings.RAS:=(dramtlr shr 15) and $F;

   //Print 64 or 128 bits mode
   //If DIMM1 & DIMM3 or DIMM1 & DIMM2 populated, than Dual Channel.

   if (((dimm3p and 1)+(dimm2p and 1) = 2) or ((dimm3p and 1)+(dimm1p and 1) = 2)) then gRAMInfo.DRAMCnls:='Dual'
  else gRAMInfo.DRAMCnls:='Single';

  gRAMInfo.DRAMType:='DDR-SDRAM'
end;

//AMD64 Methods
procedure poll_fsb_amd64(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
  dramchr, temp: DWord;
  clockratio: single;
begin
  GetInstance.IPCIIORef.GetPCIRDWord(0, 24, 2, $94, dramchr);
  temp:=(dramchr shr 20) and $7;
   clockratio:=Mult;

  case temp of
    $0:   clockratio:=trunc(Mult*2.0);
      $2:   clockratio:=trunc((Mult*3.0/2.0)+0.81);
      $4: clockratio:=trunc((Mult*4.0/3.0)+0.81);
      $5: clockratio:=trunc((Mult*6.0/5.0)+0.81);
      $6: clockratio:=trunc((Mult*10.0/9.0)+0.81);
      $7: clockratio:=trunc(Mult+0.81);
  end;

  gRAMInfo.DRAMClock:=lCPUClock/clockratio;

  gRAMInfo.DRAMCoef:='CPU/'+IntToStr(trunc(clockratio));
end;

procedure poll_timings_amd64(var Timings: tTimings; var gRAMInfo: tGRAMInfo);
var
  dramtlr, dramclr, temp: DWord;
begin
  GetInstance.IPCIIORef.GetPCIRDWord(0, 24, 2, $88, dramtlr);
   GetInstance.IPCIIORef.GetPCIRDWord(0, 24, 2, $90, dramclr);

  //CAS Latency (tCAS)
   temp:=dramtlr and $7;
  if (temp = $1) then Timings.CAS:=2
  else if (temp = $2) then Timings.CAS:=3
  else if (temp = $5) then Timings.CAS:=2.5;

   //RAS-To-CAS (tRCD)
   Timings.RCD:=(dramtlr shr 12) and $7;

   //RAS Precharge (tRP)
   Timings.RP:=(dramtlr shr 24) and $7;

   //RAS Active to precharge (tRAS)
   Timings.RAS:=(dramtlr shr 20) and $F;

   if (((dramclr shr 16) and 1) = 1) then gRAMInfo.DRAMCnls:='Dual'
  else gRAMInfo.DRAMCnls:='Single';

  gRAMInfo.DRAMType:='DDR-SDRAM'
end;

//nVidia nForce 4 SLI Intel Edition
procedure poll_fsb_nf4ie(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
   mratio, nratio: byte;
   reg60: DWord;
  reg74: Word;
  DRAMRatio: double;
begin

   //Find dramratio
   GetInstance.IPCIIORef.GetPCIRWord(0, 0, 2, $74, reg74);
   GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 2, $60, reg60);
   mratio:=reg74 and $F;
   nratio:=(reg74 shr 4) and $F;

   //If M or N = 0, then M or N = 16
   if (mratio = 0) then mratio:=16;
   if (nratio = 0) then nratio:=16;

   //Check if synchro or pseudo-synchro mode
   if (((reg60 shr 22) and 1) = 1) then DRAMRatio:=1
  else DRAMRatio:=nratio/mratio;

  gRAMInfo.DRAMClock:=FSB*DRAMRatio;

  if (DRAMRatio = 1) then gRAMInfo.DRAMCoef:='1:1'
  else gRAMInfo.DRAMCoef:=IntToStr(mratio)+':'+IntToStr(nratio);
end;

procedure poll_timings_nf4ie(var Timings: tTimings; var gRAMInfo: tGRAMInfo);
var
  regd0, reg8c, reg9c: DWord;
  reg80: byte;
begin
   //Now, read Registers
   GetInstance.IPCIIORef.GetPCIRDWord( 0, 1, 1, $D0, regd0);
   GetInstance.IPCIIORef.GetPCIRByte( 0, 1, 1, $80, reg80);
   GetInstance.IPCIIORef.GetPCIRDWord( 0, 1, 0, $8C, reg8c);
   GetInstance.IPCIIORef.GetPCIRDWord( 0, 1, 0, $9C, reg9c);

  //Then, detect timings
   Timings.CAS:=(regd0 shr 4) and $7;
   Timings.RCD:=(reg8c shr 24) and $F;
   Timings.RP:=(reg9c shr 8) and $F;
   Timings.RAS:=(reg8c shr 16) and $3F;

   if ((reg80 and $3) <> 0) then gRAMInfo.DRAMCnls:='Dual'
  else gRAMInfo.DRAMCnls:='Single';

  gRAMInfo.DRAMType:='DDRII-SDRAM'
end;


//Intel i875 Methods

procedure poll_fsb_i875(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);

var

  smfs: DWord;

  mchcfg: Word;

  DRAMRatio: single;

begin

   GetInstance.IPCIIORef.GetPCIRWord(0, 0, 0, $C6, mchcfg);

   smfs:=(mchcfg shr 10) and 3;


  DRAMRatio:=1;

  gRAMInfo.DRAMCoef:='1:1';

  if ((mchcfg and 3) = 3) then begin DRAMRatio:=1; gRAMInfo.DRAMCoef:='1:1'; end;

   if ((mchcfg and 3) = 2) then

  begin

      if (smfs = 2) then begin DRAMRatio:=1; gRAMInfo.DRAMCoef:='1:1'; end;
      if (smfs = 1) then begin DRAMRatio:=1.25; gRAMInfo.DRAMCoef:='5:4'; end;
      if (smfs = 0) then begin DRAMRatio:=1.5; gRAMInfo.DRAMCoef:='3:2'; end;
   end;

  if ((mchcfg and 3) = 1) then

  begin

    if (smfs = 2) then begin DRAMRatio:=0.6666666666; gRAMInfo.DRAMCoef:='2:3'; end;
      if (smfs = 1) then begin DRAMRatio:=0.8; gRAMInfo.DRAMCoef:='4:5'; end;
      if (smfs = 0) then begin DRAMRatio:=1; gRAMInfo.DRAMCoef:='1:1'; end;
   end;
   if ((mchcfg and 3) = 0) then begin DRAMRatio:=0.75; gRAMInfo.DRAMCoef:='3:4'; end;


  gRAMInfo.DRAMClock:=FSB/DRAMRatio;

end;


procedure poll_timings_i875(var Timings: tTimings; var gRAMInfo: tGRAMInfo);

var

  dev6, dev62, temp: DWord;

  tmp1, tmp2: DWord;

begin

   //Read the MMR Base Address & Define the pointer

   GetInstance.IPCIIORef.GetPCIRDWord(0, 6, 0, $10, dev6);


   //Now, the PAT ritual ! (Kant and Luciano will love this)

   GetInstance.IPCIIORef.GetPCIRDWord(0, 6, 0, $40, dev62);

  tmp2:=GetInstance.MemReadLong(dev6+$68);
  tmp1:=GetInstance.MemReadLong(dev6+$60);

  if (((dev62 and $3) = 0) and (((tmp2 shr 14) and 1) = 1)) then gRAMInfo.DRAMAccel:='Enabled'
  else gRAMInfo.DRAMAccel:='Disabled';


   //CAS Latency (tCAS)

   temp:=(tmp1 shr 5) and $3;
   if (temp = $0) then Timings.CAS:=2.5
  else if (temp = $1) then Timings.CAS:=2
  else Timings.CAS:=3;

   //RAS-To-CAS (tRCD)
   temp:=(tmp1 shr 2) and $3;
   if (temp = $0) then Timings.RCD:=4
  else if (temp = $1) then Timings.RCD:=3
  else Timings.RCD:= 2;

   //RAS Precharge (tRP)
   temp:=tmp1 and $3;
   if (temp = $0) then Timings.RP:=4
  else if (temp = $1) then Timings.RP:=3
  else Timings.RP:=2;

   //RAS Active to precharge (tRAS)
   temp:=(tmp1 shr 7) and $7;
   Timings.RAS:=10-temp;


  //64 or 128 bits mode

   if (((tmp2 shr 21) and 3) > 0) then gRAMInfo.DRAMCnls:='Dual'

  else gRAMInfo.DRAMCnls:='Single';

  gRAMInfo.DRAMType:='DDR-SDRAM'
end;

//Intel i925 Methods
procedure poll_fsb_i925(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
  mchcfg, mchcfg2, dev0, drc, idetect, tmp: DWord;
  DRAMRatio: single;
begin
   GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 0, $02, idetect);
  idetect:=(idetect shr 16) and $FFFF;

   //Find dramratio
   GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 0, $44, dev0);
   dev0:=dev0 and $FFFFC000;
  tmp:=GetInstance.MemReadLong(dev0+$C00);
   mchcfg:=tmp and $FFFF;
  tmp:=GetInstance.MemReadLong(dev0+$120);
   drc:=tmp and $FFFF;
   DRAMRatio:=1;
  gRAMInfo.DRAMCoef:='1:1';

  mchcfg2:=(mchcfg shr 4) and 3;

   if ((drc and 3) <> 2) then
  begin
      // We are in DDR1 Mode
      if (mchcfg2 = 1) then begin DRAMRatio:=0.8; gRAMInfo.DRAMCoef:='5:4'; end
    else begin DRAMRatio:=1; gRAMInfo.DRAMCoef:='1:1'; end;
  end
  else begin
      // We are in DDR2 Mode
      if (((mchcfg shr 2) and 1) = 1) then
    begin
         // We are in FSB1066 Mode
         if (mchcfg2 = 2) then begin DRAMRatio:=0.75; gRAMInfo.DRAMCoef:='4:3'; end
      else begin DRAMRatio:=1; gRAMInfo.DRAMCoef:='1:1'; end;
    end
    else
         case mchcfg2 of
        1: begin DRAMRatio:=0.66667; gRAMInfo.DRAMCoef:='3:2'; end;
            2: if (idetect<>$2590) then begin DRAMRatio:=1; gRAMInfo.DRAMCoef:='1:1'; end
           else begin DRAMRatio:=1.5; gRAMInfo.DRAMCoef:='2:3'; end;
            3: begin
                  // Checking for FSB533 Mode & Alviso
                  if ((mchcfg and 1) = 0) then begin DRAMRatio:=1.33334; gRAMInfo.DRAMCoef:='3:4'; end
                  else if (idetect = $2590) then begin DRAMRatio:=2; gRAMInfo.DRAMCoef:='2:1'; end
                  else begin DRAMRatio:=1.5; gRAMInfo.DRAMCoef:='2:3'; end;
        end;
        end
  end;
  gRAMInfo.DRAMClock:=FSB*DRAMRatio;
end;

procedure poll_timings_i925(var Timings: tTimings; var gRAMInfo: tGRAMInfo);
var
  dev0, drt, drc, dcc, idetect, temp, tmp: DWord;
begin
   //Now, read MMR Base Address
   GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 0, $44, dev0);
   GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 0, $02, idetect);
  idetect:=(idetect shr 16) and $FFFF;
   dev0:=dev0 and $FFFFC000;

   //Set pointer for DRT
  tmp:=GetInstance.MemReadLong(dev0+$114);
   drt:=tmp and $FFFFFFFF;

   //Set pointer for DRC
  tmp:=GetInstance.MemReadLong(dev0+$120);
   drc:=tmp and $FFFFFFFF;

   //Set pointer for DCC
  tmp:=GetInstance.MemReadLong(dev0+$200);
   dcc:=tmp and $FFFFFFFF;

   //CAS Latency (tCAS)
   temp:=(drt shr 8) and $3;

  if ((drc and 3) = 2) then
  begin
      // Timings DDR-II
    gRAMInfo.DRAMType:='DDRII-SDRAM';
      if (temp = $0) then Timings.CAS:=5
      else if (temp = $1) then Timings.CAS:=4
      else Timings.CAS:=3;
  end
  else begin
      // Timings DDR-I
    gRAMInfo.DRAMType:='DDR-SDRAM';
      if (temp = $0) then Timings.CAS:=3
      else if (temp = $1) then Timings.CAS:=2.5
      else Timings.CAS:=2;
   end;

   //RAS-To-CAS (tRCD)
  Timings.RCD:=((drt shr 4) and $3)+2;

   //RAS Precharge (tRP)
  Timings.RP:=(drt and $3)+2;

   //RAS Active to precharge (tRAS)
   //If Lakeport, than change tRAS computation (Thanks to CDH, again)
   if (idetect = $2770) or (idetect = $2774) then Timings.RAS:=(drt shr 19) and $1F
   else Timings.RAS:=(drt shr 20) and $F;

   temp:=dcc and $3;
   if (temp = 1) then gRAMInfo.DRAMCnls:='Dual'
   else if (temp = 2) then gRAMInfo.DRAMCnls:='Dual'
   else gRAMInfo.DRAMCnls:='Single';
end;

//Intel i945 Methods
procedure poll_fsb_i945(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
   mchcfg, dev0, tmp: DWord;
  DRAMRation: single;
begin
   //Find dramratio
   GetInstance.IPCIIORef.GetPCIRDWord(0, 0, 0, $44, dev0);
  dev0:=dev0 and $FFFFC000;
  tmp:=GetInstance.MemReadLong(dev0+$C00);
   mchcfg:=tmp and $FFFF;
  DRAMRation:=1;

  case ((mchcfg shr 4) and 7) of
    1: begin DRAMRation:=1; gRAMInfo.DRAMCoef:='1:1'; end;
      2: begin DRAMRation:=1.33334; gRAMInfo.DRAMCoef:='3:4'; end;
      3: begin DRAMRation:=1.66667; gRAMInfo.DRAMCoef:='3:5'; end;
      4: begin DRAMRation:=2; gRAMInfo.DRAMCoef:='1:2'; end;
  end;

  gRAMInfo.DRAMClock:=FSB*DRAMRation;
end;

//KT266 Methods
procedure poll_fsb_kt266(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
  reg69: Byte;
begin
  GetInstance.IPCIIORef.GetPCIRByte(0, 0, 0, $69, reg69);
  reg69:=(reg69 shr 6) and $3;

  case reg69 of
    0: begin gRAMInfo.DRAMCoef:='1:1'; gRAMInfo.DRAMClock:=FSB; end;
    1: begin gRAMInfo.DRAMCoef:='FSB+33'; gRAMInfo.DRAMClock:=FSB+33; end;
    2: begin gRAMInfo.DRAMCoef:='FSB-33'; gRAMInfo.DRAMClock:=FSB-33; end;
    3: begin gRAMInfo.DRAMCoef:='FSB+66'; gRAMInfo.DRAMClock:=FSB+66; end;
  end;
end;

procedure poll_timings_kt266(var Timings: tTimings; var gRAMInfo: tGRAMInfo);
var
  reg60, reg64: Byte;
begin
  GetInstance.IPCIIORef.GetPCIRByte(0, 0, 0, $60, reg60);
  GetInstance.IPCIIORef.GetPCIRByte(0, 0, 0, $64, reg64);

  //CAS Latency (tCAS)
  reg60:=reg60 and $F;
  if (reg60 = 0) then //SDR-SDRAM
  begin
    gRAMInfo.DRAMType:='SDR-SDRAM';
    case ((reg64 shr 4) and $3) of
      0: Timings.CAS:=1;
      1: Timings.CAS:=2;
      2: Timings.CAS:=3;
    end;
  end
  else begin  //DDR-SDRAM
    gRAMInfo.DRAMType:='DDR-SDRAM';
    case ((reg64 shr 4) and $3) of
      1: Timings.CAS:=2;
      2: Timings.CAS:=2.5;
      3: Timings.CAS:=3;
    end;
  end;

    //RAS-To-CAS (tRCD)
  if ((reg64 shr 2) and $1) = 1 then Timings.RCD:=3
  else Timings.RCD:=2;

   //RAS Precharge (tRP)
  if ((reg64 shr 7) and $1) = 1 then Timings.RP:=3
  else Timings.RP:=2;

  //RAS Active to precharge (tRAS)
   if ((reg64 shr 6) and $1) = 1 then Timings.RAS:=6
  else Timings.RAS:=5;
end;

//CN333 Methods
procedure poll_fsb_cn333(lCPUClock, FSB: double; Mult: single; var gRAMInfo: tGRAMInfo);
var
  reg68: Byte;
begin
  GetInstance.IPCIIORef.GetPCIRByte(0, 0, 3, $68, reg68);
  reg68:=reg68 and $F;

  case reg68 of
    0: begin gRAMInfo.DRAMCoef:='1:1'; gRAMInfo.DRAMClock:=FSB; end;
    1: begin gRAMInfo.DRAMCoef:='FSB+33'; gRAMInfo.DRAMClock:=FSB+33; end;
    5: begin gRAMInfo.DRAMCoef:='FSB+66'; gRAMInfo.DRAMClock:=FSB+66; end;
  end;
end;

procedure poll_timings_cn333(var Timings: tTimings; var gRAMInfo: tGRAMInfo);
var
  reg56: Byte;
begin
  GetInstance.IPCIIORef.GetPCIRByte(0, 0, 3, $56, reg56);

  //CAS Latency (tCAS)
  Timings.CAS:=(((reg56 shr 4) and 3)+3)/2;

  //RAS-To-CAS (tRCD)
  Timings.RCD:=((reg56 shr 2) and 3)+2;

  //RAS Precharge (tRP)
  Timings.RP:=(reg56 and 3)+2;

  //RAS Active to precharge (tRAS)
  Timings.RAS:=((reg56 shr 6) and 3)+6;
end;

const
  KnownControllers = 27;
  
var
  Controllers: array[1..KnownControllers] of Memory_Controller =
  (
    //AMD
    (VendorID: $1022; DeviceID: $1100; name: 'AMD 8000';  tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $1022; DeviceID: $7454; name: 'AMD 8000';  tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    //ALI
    (VendorID: $10b9; DeviceID: $1687; name: 'ALI M1687'; tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $10b9; DeviceID: $1689; name: 'ALI M1689'; tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $10b9; DeviceID: $1695; name: 'ALI M1695'; tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    //ATI
    (VendorID: $1002; DeviceID: $5950; name: 'ATI RS482'; tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    //nVidia
    (VendorID: $10de; DeviceID: $01A4; name: 'nVidia nForce';             tested: 0; GetFSBMethod: nil; GetTmngsMethod: nil; SetupECCMethod: nil),
    (VendorID: $10de; DeviceID: $01E0; name: 'nVidia nForce2 SPP';        tested: 0; GetFSBMethod: poll_fsb_nf2; GetTmngsMethod: poll_timings_nf2; SetupECCMethod: nil),
    (VendorID: $10de; DeviceID: $00D1; name: 'nVidia nForce3';            tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $10de; DeviceID: $00E1; name: 'nVidia nForce3 250';        tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $10de; DeviceID: $005E; name: 'nVidia nForce4';            tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $10de; DeviceID: $0071; name: 'nForce4 SLI Intel Edition'; tested: 0; GetFSBMethod: poll_fsb_nf4ie; GetTmngsMethod: poll_timings_nf4ie; SetupECCMethod: nil),
    //VIA
    (VendorID: $1106; DeviceID: $3099; name: 'VIA KT266(A)/KT333';  tested: 0; GetFSBMethod: poll_fsb_kt266; GetTmngsMethod: poll_timings_kt266; SetupECCMethod: nil),
    (VendorID: $1106; DeviceID: $3123; name: 'VIA CLE266';          tested: 0; GetFSBMethod: poll_fsb_kt266; GetTmngsMethod: poll_timings_kt266; SetupECCMethod: nil),
    (VendorID: $1106; DeviceID: $0259; name: 'VIA CN333';           tested: 0; GetFSBMethod: poll_fsb_cn333; GetTmngsMethod: poll_timings_cn333; SetupECCMethod: nil),
    (VendorID: $1106; DeviceID: $3188; name: 'VIA K8T800';          tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $1106; DeviceID: $0282; name: 'VIA K8T800Pro';       tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    (VendorID: $1106; DeviceID: $3238; name: 'VIA K8T890';          tested: 0; GetFSBMethod: poll_fsb_amd64; GetTmngsMethod: poll_timings_amd64; SetupECCMethod: nil),
    //Intel
    (VendorID: $8086; DeviceID: $2588; name: 'Intel E7221';     tested: 0; GetFSBMethod: nil{poll_fsb_i925}; GetTmngsMethod: nil{poll_timings_i925}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2570; name: 'Intel i848/i865'; tested: 0; GetFSBMethod: nil{poll_fsb_i875}; GetTmngsMethod: nil{poll_timings_i875}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2578; name: 'Intel i875P';     tested: 0; GetFSBMethod: nil{poll_fsb_i875}; GetTmngsMethod: nil{poll_timings_i875}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $3340; name: 'Intel i855PM';    tested: 0; GetFSBMethod: nil;                GetTmngsMethod: nil;               SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2580; name: 'Intel i915P/G';   tested: 0; GetFSBMethod: nil{poll_fsb_i925}; GetTmngsMethod: nil{poll_timings_i925}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2590; name: 'Intel i915PM/GM'; tested: 0; GetFSBMethod: nil{poll_fsb_i925}; GetTmngsMethod: nil{poll_timings_i925}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2584; name: 'Intel i925X/XE';  tested: 0; GetFSBMethod: nil{poll_fsb_i925}; GetTmngsMethod: nil{poll_timings_i925}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2770; name: 'Intel i945P/G';   tested: 0; GetFSBMethod: nil{poll_fsb_i945}; GetTmngsMethod: nil{poll_timings_i925}; SetupECCMethod: nil),
    (VendorID: $8086; DeviceID: $2774; name: 'Intel i955X';     tested: 0; GetFSBMethod: nil{poll_fsb_i945}; GetTmngsMethod: nil{poll_timings_i925}; SetupECCMethod: nil)
  );


constructor cMemory.Create;
begin
  inherited Create;
  fCtrl_Info.index:=0;

  fCtrl_Info.dwBus:=0;
  fCtrl_Info.dwDev:=0;
  fCtrl_Info.dwFunc:=0;

  DetectMemCtrl;
end;

procedure cMemory.DetectMemCtrl;
var
  VendorID, DeviceID: DWord;
  pdata: DWord;
  i: byte;
begin
  GetInstance.IPCIIORef.GetPCIRDWord(fCtrl_Info.dwBus, fCtrl_Info.dwDev, fCtrl_Info.dwFunc, 0, pdata);
  VendorID:=Word(pdata);
  DeviceID:=Word(pdata shr 16);

  for i:=Low(Controllers) to High(Controllers) do
    if ((Controllers[i].VendorID = VendorID) and (Controllers[i].DeviceID = DeviceID)) then
    begin
      fCtrl_Info.index:=i;
      break;
    end;
end;

function cMemory.GetPhysMemSize: DWord;
var  
 memStatus: TMemoryStatus;
begin
  memStatus.dwLength:=sizeOf(memStatus);
  GlobalMemoryStatus(memStatus);
  result:=trunc(memStatus.dwTotalPhys/1048576)+1;
end;


procedure cMemory.FillMemCtrlInfo(lCPUClock, FSB: double; Mult: single);
begin
  if fCtrl_Info.index<=0 then exit;

  fgRAMInfo.RamSize:=GetPhysMemSize;

  if Assigned(Controllers[fCtrl_Info.index].GetFSBMethod) then
        Controllers[fCtrl_Info.index].GetFSBMethod(lCPUClock, FSB, Mult, fgRAMInfo);

  if Assigned(Controllers[fCtrl_Info.index].GetTmngsMethod) then
        Controllers[fCtrl_Info.index].GetTmngsMethod(fTimings, fgRAMInfo);

  //ShowMessage(format('%x', [oHWIO.MemReadLong($20)]));
  //oHWIO.MemReadLong($5)
end;

destructor cMemory.Destroy;
begin
  inherited Destroy;
end;

end.

Report for Muetze1 from pci 32 program,is this usefull?

[delphi] Address 1 is a Memory Address (anywhere in 0-4Gb) : FFEFF400h
System IRQ 11, INT# A
Expansion ROM of 64Kb decoded by this card (Currently disabled)
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D1, D2, D3hot, D3cold
PME# signalling is currently enabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 375mA

Bus 0 (PCI), Device Number 15, Device Function 0
Vendor 1106h VIA Technologies Inc
Device 3149h VIA SATA RAID Controller
Command 0007h (I/O Access, Memory Access, BusMaster)
Status 0290h (Has Capabilities List, Supports Back-To-Back Trans., Medium Timin
g)
Revision 80h, Header Type 80h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
PCI Class Storage, type RAID
Subsystem ID 31491849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 0 is an I/O Port : 0000EC00h
Address 1 is an I/O Port : 0000E800h
Address 2 is an I/O Port : 0000E400h
Address 3 is an I/O Port : 0000E000h
Address 4 is an I/O Port : 0000DC00h
Address 5 is an I/O Port : 0000D800h
System IRQ 10, INT# B
New Capabilities List Present:
Power Management Capability, Version 1.1
Does not support low power State D1 or D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)

Bus 0 (PCI), Device Number 15, Device Function 1
Vendor 1106h VIA Technologies Inc
Device 0571h VT82xxxx EIDE Controller (All VIA Chipsets)
Command 0007h (I/O Access, Memory Access, BusMaster)
Status 0290h (Has Capabilities List, Supports Back-To-Back Trans., Medium Timin
g)
Revision 06h, Header Type 00h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
PCI Class Storage, type IDE (ATA)
PCI EIDE Controller Features :
BusMaster EIDE is supported
Primary Channel is at I/O Port 01F0h and IRQ 14
Secondary Channel is at I/O Port 0170h and IRQ 15
Subsystem ID 05711849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 4 is an I/O Port : 0000FC00h
New Capabilities List Present:
Power Management Capability, Version 1.1
Does not support low power State D1 or D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)

Bus 0 (PCI), Device Number 16, Device Function 0
Vendor 1106h VIA Technologies Inc
Device 3038h VT82xxxxx UHCI USB 1.1 Controller (All VIA Chipsets)
Command 0017h (I/O Access, Memory Access, BusMaster, MemWrite+Invalidate)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 81h, Header Type 80h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Serial, type USB (UHCI)
Subsystem ID 30381849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 4 is an I/O Port : 0000C000h
System IRQ 11, INT# A
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D0, D1, D2, D3hot, D3cold
PME# signalling is currently disabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 375mA

Bus 0 (PCI), Device Number 16, Device Function 1
Vendor 1106h VIA Technologies Inc
Device 3038h VT82xxxxx UHCI USB 1.1 Controller (All VIA Chipsets)
Command 0017h (I/O Access, Memory Access, BusMaster, MemWrite+Invalidate)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 81h, Header Type 80h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Serial, type USB (UHCI)
Subsystem ID 30381849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 4 is an I/O Port : 0000C400h
System IRQ 11, INT# A
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D0, D1, D2, D3hot, D3cold
PME# signalling is currently disabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 375mA

Bus 0 (PCI), Device Number 16, Device Function 2
Vendor 1106h VIA Technologies Inc
Device 3038h VT82xxxxx UHCI USB 1.1 Controller (All VIA Chipsets)
Command 0017h (I/O Access, Memory Access, BusMaster, MemWrite+Invalidate)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 81h, Header Type 80h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Serial, type USB (UHCI)
Subsystem ID 30381849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 4 is an I/O Port : 0000C800h
System IRQ 10, INT# B
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D0, D1, D2, D3hot, D3cold
PME# signalling is currently disabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 375mA

Bus 0 (PCI), Device Number 16, Device Function 3
Vendor 1106h VIA Technologies Inc
Device 3038h VT82xxxxx UHCI USB 1.1 Controller (All VIA Chipsets)
Command 0017h (I/O Access, Memory Access, BusMaster, MemWrite+Invalidate)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 81h, Header Type 80h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Serial, type USB (UHCI)
Subsystem ID 30381849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 4 is an I/O Port : 0000CC00h
System IRQ 10, INT# B
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D0, D1, D2, D3hot, D3cold
PME# signalling is currently disabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 375mA

Bus 0 (PCI), Device Number 16, Device Function 4
Vendor 1106h VIA Technologies Inc
Device 3104h VT6202/12 USB 2.0 Enhanced Host Controller
Command 0017h (I/O Access, Memory Access, BusMaster, MemWrite+Invalidate)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 86h, Header Type 80h, Bus Latency Timer 20h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Serial, type USB 2.0 (EHCI)
Subsystem ID 31041849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 0 is a Memory Address (anywhere in 0-4Gb) : FFEFF800h
System IRQ 5, INT# C
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D0, D1, D2, D3hot, D3cold
PME# signalling is currently disabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 375mA

Bus 0 (PCI), Device Number 17, Device Function 0
Vendor 1106h VIA Technologies Inc
Device 3227h VT8237 PCI to ISA Bridge
Command 0087h (I/O Access, Memory Access, BusMaster, Wait Cycles)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 00h, Header Type 80h, Bus Latency Timer 00h
Self test 00h (Self test not supported)
PCI Class Bridge, type PCI to ISA
Subsystem ID 32271849h Unknown
Subsystem Vendor 1849h ASRock Inc
New Capabilities List Present:
Power Management Capability, Version 1.1
Does not support low power State D1 or D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)

Bus 0 (PCI), Device Number 17, Device Function 5
Vendor 1106h VIA Technologies Inc
Device 3059h VT8233/A AC'97 Enhanced Audio Controller
Command 0001h (I/O Access)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 60h, Header Type 00h, Bus Latency Timer 00h
Self test 00h (Self test not supported)
PCI Class Multimedia, type Audio
Subsystem ID 97611849h VT8233 AC'97 Enhanced Audio Controller (Guess Only!)
Subsystem Vendor 1849h ASRock Inc
Address 0 is an I/O Port : 0000D000h
System IRQ 5, INT# C
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)

Bus 0 (PCI), Device Number 18, Device Function 0
Vendor 1106h VIA Technologies Inc
Device 3065h VT6102 Rhine II Fast Ethernet Adapter
Command 0117h (I/O Access, Memory Access, BusMaster, MemWrite+Invalidate, Syste
m Errors)
Status 0210h (Has Capabilities List, Medium Timing)
Revision 78h, Header Type 00h, Bus Latency Timer 20h
Minimum Bus Grant 03h, Maximum Bus Latency 08h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Network, type Ethernet
Subsystem ID 30651849h Unknown
Subsystem Vendor 1849h ASRock Inc
Address 0 is an I/O Port : 0000D400h
Address 1 is a Memory Address (anywhere in 0-4Gb) : FFEFFC00h
System IRQ 11, INT# A
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Supports PME# signalling from mode(s) D0, D1, D2, D3hot, D3cold
PME# signalling is currently enabled
Current Power State : D0 (Device operational, no power saving)
3.3v AUX Current required : 0mA (Self powered)

Bus 1 (AGP), Device Number 0, Device Function 0
Vendor 1002h ATI Technologies Inc
Device 7280h Unknown
Command 0107h (I/O Access, Memory Access, BusMaster, System Errors)
Status 02B0h (Has Capabilities List, Supports 66MHz, Supports Back-To-Back Tran
s., Medium Timing)
Revision 9Ah, Header Type 80h, Bus Latency Timer FFh
Minimum Bus Grant 08h, Maximum Bus Latency 00h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Display, type VGA
Subsystem ID E190174Bh Unknown
Subsystem Vendor 174Bh PC Partner Ltd
Address 0 is a Memory Address (anywhere in 0-4Gb, Prefetchable) : C0000000h
Address 1 is an I/O Port : 0000A800h
Address 2 is a Memory Address (anywhere in 0-4Gb) : FFDF0000h
System IRQ 11, INT# A
Expansion ROM of 128Kb decoded by this card (Currently disabled)
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)
AGP Capability, Version 3.0 (AGP 8x and 4x, core register support)
AGP Speed(s) Supported : 4x 8x
FW Transfers Supported : Yes
>4Gb Address Space Supported : No
Sideband Addressing Supported : Yes
AGP v3.0 Operation Mode Available : Yes
Isosynchronous Transactions Supported : No
Maximum Command Queue Length : 256 bytes
AGP Speed Selected : 8x
FW Transfers Enabled : Yes
>4Gb Address Space Enabled : No
AGP Enabled : Yes
Sideband Addressing Enabled : Yes
AGP v3.0 Operation Mode : Enabled
Current Command Queue Length : 32 bytes
Message Signalled Interrupt Capability
MSI is disabled
MSI function can generate 64-bit addresses

Bus 1 (AGP), Device Number 0, Device Function 1
Vendor 1002h ATI Technologies Inc
Device 72A0h Unknown
Command 0007h (I/O Access, Memory Access, BusMaster)
Status 02B0h (Has Capabilities List, Supports 66MHz, Supports Back-To-Back Tran
s., Medium Timing)
Revision 9Ah, Header Type 00h, Bus Latency Timer 20h
Minimum Bus Grant 08h, Maximum Bus Latency 00h
Self test 00h (Self test not supported)
Cache line size 32 Bytes (8 DWords)
PCI Class Display, type Other
Subsystem ID E191174Bh Unknown
Subsystem Vendor 174Bh PC Partner Ltd
Address 0 is a Memory Address (anywhere in 0-4Gb) : FFDE0000h
New Capabilities List Present:
Power Management Capability, Version 1.1
Supports low power State D1
Supports low power State D2
Does not support PME# signalling
Current Power State : D0 (Device operational, no power saving)


IRQ Summary: IRQs 5,10,11,14,15 are used by PCI devices
Shared IRQs: IRQ 5 is shared by 2 PCI Devices
IRQ 10 is shared by 3 PCI Devices
IRQ 11 is shared by 5 PCI Devices


[delphi]